VLSI Design Flow: RTL to GDS

A free NPTEL video course of 54 lectures. Taught by Prof. Sneh Saurabh (IIIT Delhi).

Lectures include:

• Basic Concepts of Integrated Circuit - I
• Basic Concepts of Integrated Circuit - II
• Overview of VLSI Design Flow - I
• Overview of VLSI Design Flow - II
• Tutorial 1
• Overview of VLSI Design Flow - III
• Overview of VLSI Design Flow - IV
• Overview of VLSI Design Flow - V
• Overview of VLSI Design Flow - VI
• Introduction to TCL
• Hardware Modeling: Introduction to Verilog-I
• Hardware Modeling: Introduction to Verilog-II
• Functional Verification using Simulation
• High-level synthesis using Bambu - Tutorial 3
• RTL Synthesis- Part I