Hardware Modeling using Verilog

Describing hardware in code

This course is about the modeling side of hardware design. It begins with how designs are represented and with the main VLSI design styles, then turns to the Verilog language itself, so the reasoning comes before the syntax.

What the lectures cover

• Verilog language features, taught across several lectures
• Operators and the modeling examples that use them
• Description styles for hardware and how they differ
• Procedural assignment, with worked examples

Who it suits

Students who prefer a lecture-led, theory-first route into Verilog. Because the design styles come first, the course helps you judge when a given modeling style fits a piece of hardware, not only how to write it. Pair it with a hands-on Verilog course if you want to practice the constructs as you go.