Verilog Full Course for Beginners | Learn Verilog from Scratch (3 Hours)

Learn Verilog from scratch in this complete 3-hour course for beginners. Covers HDL basics, modules and instantiation, data types, operators, gate-level, dataflow and behavioral modeling, tasks and functions, and writing a testbench. Ideal for ECE students and anyone starting VLSI.

Complete Verilog notes:
https://drive.google.com/file/d/191mcKOGC6BpLyZNvb1Q9stq9-hlroke1/view?usp=sharing

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00:00 Introduction to Verilog HDL
04:00 Verilog vs. VHDL
06:00 Levels of Abstraction in Verilog
14:45 Modules and Basic Verilog Syntax
17:40 Module Instantiation and Hierarchy
23:25 Keywords and Comments
25:15 Simulation vs. Synthesis
28:20 Top-Down and Bottom-Up Design
31:00 Verilog Data Types
34:45 Port Assignments
36:00 Wire and Net Data Types
39:40 Number Representation and Extensions
44:40 Register Data Types: Reg, Integer, Real and Time
50:45 Vectors, Arrays and Memories
56:00 Parameters and Strings
59:20 Verilog Operators
01:00:00 Arithmetic Operators
01:03:50 Logical and Bitwise Operators
01:07:35 Equality and Relational Operators
01:12:50 Reduction and Shift Operators
01:16:30 Concatenation and Conditional Operators
01:19:35 Operator Precedence and Practice Questions
01:28:55 Gate-Level Modeling and Gate Primitives
01:35:20 Gate Delays
01:40:40 Continuous Assignment
01:44:20 Delay in Continuous Assignment
01:54:35 Procedural Assignments
01:55:05 Blocking vs. Non-Blocking Assignments
01:57:25 Procedural Assignment Delays
02:02:50 If-Else Statements
02:04:05 Case Statements
02:05:15 Looping Constructs
02:12:20 Verilog System Tasks
02:21:05 Compiler Directives
02:23:50 Tasks and Functions
02:38:20 Testbench Writing Formats
02:41:35 Testbench Examples
02:59:00 Conclusion

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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar

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