Verilog HDL complete course

A 41-video playlist by ALL ABOUT VLSI, about 19 hours of video in total.

Videos in this playlist include:

• Introduction to Verilog: Modules, Number Representations & Comments | Free DV Course|All about VLSI
• Verilog Data Types Explained | reg, net, integer, real, time | Verilog Tutorial for Beginners
• Port Connection Rules in Verilog | Connect by Order vs Connect by Name Explained
• Introduction to Gate Level Modeling in Verilog | Getting Started with Vivado Tool Interface
• Verilog Code for Full Adder using Half Adder | Gate Level Modeling | All about VLSI ||
• BCD and Ripple Carry Adder (RCA) Using GLM in Verilog | Digital Design Explained
• 2-Bit Comparator using Gate Level Modeling in Verilog | Digital Design & Verilog HDL Tutorial
• Introduction to Behavioral Modeling in Verilog | Verilog Tutorial for Beginners|| All about VLSI ||
• Operators in Verilog Part 2 | Bitwise, Relational & Equality Operators with Examples
• Logical Operators, Shift & Concatenation in Verilog | Verilog Basics Explained || All about VLSI ||
• Blocking vs Non-Blocking in Verilog | Inter vs Intra Assignment Explained || All about VLSI ||
• Verilog Event Scheduler & System Tasks Explained with Examples | Verilog full course |All about VLSI
• Verilog Practice on HDLBits | Step-by-Step Problem Solving Explained
• Event Scheduler in Verilog final part| $monitor | Behavioral Modeling with Half Adder
• Full adder and Half subtractor verilog code in behavioral modelling || Verilog full course |
• BCD Adder and Ripple Carry Adder using Behavioral Modeling | Verilog Explained Step-by-Step
• Loops & Case Statements in Verilog | MUX Design and Testbench using Case Statement Explained
• MUX and DEMUX Design in Verilog | Using if-else & case statements explained
• Encoder, Decoder & Priority Encoder in Verilog | Behavioral Modeling using CASEX || All about VLSI
• SR Latch Design in Verilog | Step-by-Step Explanation for Beginners || Verilog full course ||
• D, JK & T Latch Design in Verilog | Verilog Sequential Circuits Explained
• SISO & SIPO Design using Verilog | Verilog full course || All about VLSI ||
• PISO and PIPO Register in Verilog | Shift Register Design Explained with Code
• Universal Shift Register in Verilog | Code Development & Working Explained | Verilog Projects
• Blocking vs Non-Blocking in Verilog | MOD-4 Synchronous Up Counter Explained | Verilog for Beginners

…and 16 more videos.